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URN: urn:nbn:de:bsz:16-opus-91139
URL: http://www.ub.uni-heidelberg.de/archiv/9113
Hinweis zum Urheberrecht.
HyperTransport 3 Core: A Next Generation Host Interface with Extremely High Bandwidth
Kalisch, Benjamin ; Giese, Alexander ; Litz, Heiner ; Brüning, Ulrich
pdf-Format:
Dokument 1.pdf (1.257 KB)
Gedruckte Ausgabe:
SWD-Schlagwörter:
Computerarchitektur
Institut:
Institut f. Technische Informatik (ZITI)
DDC-Sachgruppe:
Informatik
Dokumentart:
Aufsatz
Sprache:
Englisch
Erstellungsjahr:
2009
Publikationsdatum:
03.03.2009
Kurzfassung in Englisch:
As the amount of computing power keeps increasing, host interface bandwidth to memory and input-output devices (I/O) becomes a more and more limiting factor. High speed serial host interface protocols like PCI-Express and HyperTransport (HT) have been introduced to satisfy the applications’ ever increasing demands for more bandwidth. Recent applications in the field of General Purpose Graphic Processing Units (GPGPUs) and Field Programmable Gate Array (FPGA) based coprocessors are an example. In this Paper we present a novel implementation of an FPGA based HyperTransport 3 (HT3) host interface. To the best of our knowledge it represents the very first implementation of this type. The design offers an extremely high unidirectional bandwidth of up to 2.3 GByte/s. It can be employed in arbitrary FPGA applications and then offers direct access to an AMD Opteron processor via the HT interface. To allow the development of an optimal design, we perform a complexity and requirements analysis. The result is our proposed solution which has been implemented in synthesizable Hardware Description Language (HDL) code. Microbenchmarks are presented to show the feasibility and high performance of the design.
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