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URN: urn:nbn:de:bsz:16-opus-91152
URL: http://www.ub.uni-heidelberg.de/archiv/9115
Hinweis zum Urheberrecht.
A general purpose HyperTransport-based Application Accelerator Framework
Kramer, David ; Vogel, Thorsten ; Buchty, Rainer ; Nowak, Fabian ; Karl, Wolfgang
pdf-Format:
Dokument 1.pdf (1.148 KB)
Gedruckte Ausgabe:
SWD-Schlagwörter:
Computerarchitektur
Institut:
Institut f. Technische Informatik (ZITI)
DDC-Sachgruppe:
Informatik
Dokumentart:
Aufsatz
Sprache:
Englisch
Erstellungsjahr:
2009
Publikationsdatum:
03.03.2009
Kurzfassung in Englisch:
HyperTransport provides a flexible, low latency and high bandwidth interconnection between processors and also between processors and peripheral omponents. Therefore, the interconnection is no longer a performance bottleneck
when integrating application specific accelerators in modern computing systems. Current FPGAs providing huge computational power and permit the acceleration of
compute-intensive kernels. We therefore present a general purpose architecture based on HyperTransport and modern FPGAs to accelerate time-consuming computations. Further, we present a prototypical implementation of our architecture. Here we used an AMD Opteron-based system with the HTX Board [6] to demonstrate that common applications can benefit from available hardware accelerators. A cryptographic example showed that the encryption of files, larger then 50 kByte, can be successfully accelerated.
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