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URN: urn:nbn:de:bsz:16-opus-97962
URL: http://www.ub.uni-heidelberg.de/archiv/9796
Hinweis zum Urheberrecht.
A HyperTransport-Enabled Global Memory Model For Improved Memory Efficiency (revised 08/2009)
Young, Jeffrey ; Yalamanchili, Sudhakar ; Silla, Federico ; Duato, Jose
pdf-Format:
Dokument 1.pdf (1.448 KB)
SWD-Schlagwörter:
Computerarchitektur
Institut:
Institut f. Technische Informatik (ZITI)
DDC-Sachgruppe:
Informatik
Dokumentart:
Aufsatz
Sprache:
Englisch
Erstellungsjahr:
2009
Publikationsdatum:
31.08.2009
Bemerkung:
Aktualisierte Version des Dokuments mit der URN: urn:nbn:de:bsz:16-opus-91126,
URL: http://www.ub.uni-heidelberg.de/archiv/9112.
Kurzfassung in Englisch:
Modern data centers esenting unprecedented demands in terms of cost and energy consumption, far outpacing architectural advances. Consequently, blade designs exhibit significant cost and power inefficiencies, particularly in the memory system. We propose a HyperTransport-enabled solution called the Dynamic Partitioned Global Address Space (DPGAS) model for seamless, efficient sharing of memory across bladeare prs in a data center, leading to significant power and cost savings. This paper presents the DPGAS model, describes HyperTransport-based hardware support for the model, and assesses this model’s power and cost impact on memory intensive applications. Overall, we find that cost savings can range from 4% to 26% with power reductions ranging from 2% to 25% across a variety of fixed application configurations using server consolidation and memory throttling. The HyperTransport implementation enables these savings with an additional node latency cost of 1,690 ns latency per remote 64 byte cache line access across the blade-to-blade interconnect.
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