Product Datasheet
eSi-RAM/2PTM
Two-Port Register File SRAM
128 Words 16 Bits per word
Functional Description
The two-port register file (Table 1) generated by the VST Two Port
Register File compiler is a completely static memory device. The two-port
register file has an address port for read and an independent address port
for write (Fig.1, Table 2). The independent read and write cycles
are timed with respect to their own clocks.
During a read cycle (Table 3), the output bus values are held if
read enable is not asserted. The read enable feature is
used to save RAM power without the need for external gating.
During a write cycle WEN, WADR, and DI are sampled at the
rising edge of write clock (WCK). See Table 4.
Simultaneous read and write to different memory locations has no special
timing restrictions.
It is possible to perform a simultaneous read and write operation to the same
address in one cycle. For this, the time between WCK and RCK must be Twckrck (Fig.2).
If Twckrck is violated, there is a possibility that the Read data will be corrupted,
but the Write cycle will complete properly.
The optional test pins are not included in this instance of the RAM.
Table 1: Configuration
| Configuration | Value |
|---|
| Compiler | Two Port Register File |
| Process | L180 |
| Foundry | umc |
| Size (microns) | 134.52 by 445.52 |
| Words | 128 |
| Bits | 16 |
| Mux | 1 |
| Power Bus | o |
| Frequency | 120 |
| Power (uW/MHz) | 33.61 |
The maximum power number given in the table above is for Fast process
at 1.98 Volts and 0 Degrees C junction temperature.
