TY  - JOUR
N2  - FPGAs as reconfigurable devices play an important role in both rapid prototyping and high performance reconfigurable computing. Usually, FPGA vendors help the users with pre-designed cores, for instance for various communication protocols. However, this is only true for widely used protocols. In the use case described here, the target application may benefit from a tight integration of the FPGA in a computing system. Typical commodity protocols like PCI Express may not fulfill these demands. HyperTransport (HT), on the other hand, allows connecting directly and without intermediate bridges or protocol conversion to a processor interface. As a result, communication costs between the FPGA unit and both processor and main memory are minimal. In this paper we present an HT3 interface for Stratix IV based FPGAs, which allows for minimal latencies and high bandwidths between processor and device and main memory and device. Designs targeting a HT connection can now be prototyped in real world systems. Furthermore, this design can be leveraged for acceleration tasks, with the minimal communication costs allowing fine-grain work deployment and the use of cost-efficient main memory instead of size-limited and costly on-device memory.
A1  - Lemke, Frank
A1  - Kapferer, Sven
A1  - Giese, Alexander
A1  - Fröning, Holger
A1  - Brüning, Ulrich
Y1  - 2011///
TI  - A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing
AV  - public
ID  - heidok11588
UR  - https://archiv.ub.uni-heidelberg.de/volltextserver/11588/
ER  -