TY  - GEN
AV  - public
N2  - The increasing importance of multigigabit transceiver circuits in modern chip design calls for new methods of analyzing and integrating these challenging building blocks. This work presents a design and analysis framework basend on the SystemVerilog real number modeling ansatz. It further extends the simulation possibilities thus obtained by introducing additional higher level numeric modelling and evaluation methods to support multigigabit statistical link budgeting procedures based on the Peak Distortion Algorithm.
A1  - Thürmer, Maximilian
CY  - Heidelberg
UR  - https://archiv.ub.uni-heidelberg.de/volltextserver/23838/
ID  - heidok23838
TI  - Modelling and performance analysis of
multigigabit serial interconnects using real
number based analog verification methods
Y1  - 2018///
ER  -