eprintid: 23838
rev_number: 15
eprint_status: archive
userid: 3445
dir: disk0/00/02/38/38
datestamp: 2018-01-19 08:07:52
lastmod: 2018-01-25 10:31:13
status_changed: 2018-01-19 08:07:52
type: doctoralThesis
metadata_visibility: show
creators_name: Thürmer, Maximilian
title: Modelling and performance analysis of
multigigabit serial interconnects using real
number based analog verification methods
title_de: Modellierung und Leistungsanalyse von Multigigabit Transceivern mittels zeitdiskreten und wertkontinuierlichen, analogen Verifikationsmethoden
subjects: 004
subjects: 600
subjects: 620
divisions: 110300
adv_faculty: af-11
abstract: The increasing importance of multigigabit transceiver circuits in modern chip design calls for new methods of analyzing and integrating these challenging building blocks. This work presents a design and analysis framework basend on the SystemVerilog real number modeling ansatz. It further extends the simulation possibilities thus obtained by introducing additional higher level numeric modelling and evaluation methods to support multigigabit statistical link budgeting procedures based on the Peak Distortion Algorithm.
abstract_translated_lang: ger
date: 2018
id_scheme: DOI
id_number: 10.11588/heidok.00023838
ppn_swb: 1658918967
own_urn: urn:nbn:de:bsz:16-heidok-238385
date_accepted: 2017-11-20
advisor: HASH(0x564e1c38c388)
language: eng
bibsort: THURMERMAXMODELLINGA2018
full_text_status: public
place_of_pub: Heidelberg
citation:   Thürmer, Maximilian  (2018) Modelling and performance analysis of multigigabit serial interconnects using real number based analog verification methods.  [Dissertation]     
document_url: https://archiv.ub.uni-heidelberg.de/volltextserver/23838/1/dissertation_thuermer.pdf