eprintid: 23972
rev_number: 16
eprint_status: archive
userid: 3549
dir: disk0/00/02/39/72
datestamp: 2018-01-25 09:16:11
lastmod: 2018-01-29 09:55:48
status_changed: 2018-01-25 09:16:11
type: doctoralThesis
metadata_visibility: show
creators_name: Müller, Markus Roman
title: Digital Centric Multi-Gigabit SerDes Design and Verification
subjects: 500
subjects: 620
divisions: 110300
adv_faculty: af-11
abstract: Advances in semiconductor manufacturing still lead to ever decreasing feature sizes and constantly allow higher degrees of integration in application specific integrated circuits (ASICs). Therefore the bandwidth requirements on the external interfaces of such systems on chips (SoC) are steadily growing. Yet, as the number of pins on these ASICs is not increasing in the same pace - known as pin limitation - the bandwidth per pin has to be increased.

SerDes (Serializer/Deserializer) technology, which allows to transfer data serially at very high data rates of 25Gbps and more is a key technology to overcome pin limitation and exploit the computing power that can be achieved in todays SoCs. As such SerDes blocks together with the digital logic interfacing them form complex mixed signal systems, verification of performance and functional correctness is very challenging.

In this thesis a novel mixed-signal design methodology is proposed, which tightly couples model and implementation in order to ensure consistency throughout the design cycles and hereby accelerate the overall implementation flow. A tool flow that has been developed is presented, which integrates well into state of the art electronic design automation (EDA) environments and enables the usage of this methodology in practice.

Further, the design space of todays high-speed serial links is analyzed and an architecture is proposed, which pushes complexity into the digital domain in order to achieve robustness, portability between manufacturing processes and scaling with advanced node technologies. The all digital phase locked loop (PLL) and clock data recovery (CDR), which have been developed are described in detail.

The developed design flow was used for the implementation of the SerDes architecture in a 28nm silicon process and proved to be indispensable for future projects.
date: 2018
id_scheme: DOI
id_number: 10.11588/heidok.00023972
ppn_swb: 1659064759
own_urn: urn:nbn:de:bsz:16-heidok-239725
date_accepted: 2018-01-12
advisor: HASH(0x55611e72af98)
language: eng
bibsort: MULLERMARKDIGITALCEN2018
full_text_status: public
citation:   Müller, Markus Roman  (2018) Digital Centric Multi-Gigabit SerDes Design and Verification.  [Dissertation]     
document_url: https://archiv.ub.uni-heidelberg.de/volltextserver/23972/1/Thesis_Markus_Mueller.pdf