title: Von Neumann bottlenecks in non-von Neumann computing architectures
creator: Karasenko, Vitali
subject: ddc-004
subject: 004 Data processing Computer science
subject: ddc-530
subject: 530 Physics
description: The term "neuromorphic" refers to a broad class of computational devices that mimic various aspects of cortical information processing.  In particular, they instantiate neurons, either physically or virtually, which communicate through time-singular events called spikes.  This thesis presents a generic RTL implementation of a Point-to-Point chip interconnect protocol that is well-suited to accommodate the unique I/O requirements associated with event-based communication, especially in the case of accelerated mixed-signal neuromorphic devices.  A physical realization of such an interconnect was implemented on the most recent version of the BrainScaleS-2 architecture---the HICANN-X system---to facilitate a high-speed bi-directional connection to a host FPGA.  Event rates of up to 250MHz full-duplex as well as several stream-secured configuration and memory interface channels are transported via 8*1Gbit/s LVDS DDR serializers.  As the presented approach is entirely independent of the serializer implementation, it has applications beyond neuromorphic computing, such as enabling the separation of concerns and aiding the development of serializer-independent protocol bridges for system design.
date: 2020
type: Dissertation
type: info:eu-repo/semantics/doctoralThesis
type: NonPeerReviewed
format: application/pdf
identifier: https://archiv.ub.uni-heidelberg.de/volltextserver/28691/1/KarasenkoPhD.pdf
identifier: DOI:10.11588/heidok.00028691
identifier: urn:nbn:de:bsz:16-heidok-286910
identifier:   Karasenko, Vitali  (2020) Von Neumann bottlenecks in non-von Neumann computing architectures.  [Dissertation]     
relation: https://archiv.ub.uni-heidelberg.de/volltextserver/28691/
rights: info:eu-repo/semantics/openAccess
rights: http://archiv.ub.uni-heidelberg.de/volltextserver/help/license_urhg.html
language: eng