eprintid: 9115
rev_number: 29
eprint_status: archive
userid: 1
dir: disk0/00/00/91/15
datestamp: 2009-03-03 11:40:43
lastmod: 2016-01-17 13:14:10
status_changed: 2012-08-14 15:28:13
type: article
metadata_visibility: show
creators_name: Kramer, David
creators_name: Vogel, Thorsten
creators_name: Buchty, Rainer
creators_name: Nowak, Fabian
creators_name: Karl, Wolfgang
title: A general purpose HyperTransport-based Application Accelerator Framework
ispublished: pub
subjects: 004
divisions: 720000
cterms_swd: Computerarchitektur
abstract: HyperTransport provides a flexible, low latency and high bandwidth interconnection between processors and also between processors and peripheral  omponents. Therefore, the interconnection is no longer a performance bottleneck when integrating application specific accelerators in modern computing systems. Current FPGAs providing huge computational power and permit the acceleration of compute-intensive kernels. We therefore present a general purpose architecture based on HyperTransport and modern FPGAs to accelerate time-consuming computations. Further, we present a prototypical implementation of our architecture. Here we used an AMD Opteron-based system with the HTX Board [6] to demonstrate that common applications can benefit from available hardware accelerators. A cryptographic example showed that the encryption of files, larger then 50 kByte, can be successfully accelerated.
abstract_translated_lang: eng
date: 2009
date_type: published
id_scheme: DOI
id_number: 10.11588/heidok.00009115
portal_cluster_id: p-whtra09
portal_order: 4
ppn_swb: 1373992808
own_urn: urn:nbn:de:bsz:16-opus-91152
language: eng
bibsort: KRAMERDAVIAGENERALPU2009
full_text_status: public
citation:   Kramer, David ; Vogel, Thorsten ; Buchty, Rainer ; Nowak, Fabian ; Karl, Wolfgang  (2009) A general purpose HyperTransport-based Application Accelerator Framework.         
document_url: https://archiv.ub.uni-heidelberg.de/volltextserver/9115/1/whtra09_paper14.pdf