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The early fault analysis is mandatory for safety critical systems, which are required to operate safely even on the presence of faults. System design methodologies tackle the early design and verification of systems by allowing several abstraction for their models, but still offer only digital bit faults as fault models. Therefore we develop a signal fault model for the Transaction-Level Modeling. We extend the TLM generic payload by the signal characteristics: Voltage level, delay, slope time and glitches. In order to analyze and process these, a TLM bus model is created, with which signal faults can be detected and translated to data failures. Furthermore, inserting this bus in an acquisition system and implementing fallback modes for the bus operation, the propagation of the signal faults through the system can be assessed. Simulating this model using probability distributions for the different signal faults, 5516 faults have been generated. From these, 5143 have been recovered, 239 isolated and 134 turned into failures.
|Item Type:||Conference Item|
|Series Name:||International Workshop on the Design of Dependable Critical Systems|
|Faculties / Institutes:||Service facilities > Institut f. Technische Informatik (ZITI)|
|Subjects:||004 Data processing Computer science|
|Uncontrolled Keywords:||Signal faults, mixed signal verification, system design, fault modeling, system model|