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Applications for Packetized Memory Interfaces

Watson, Myles Glen

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Abstract

The performance of the memory subsystem has a large impact on the performance of modern computer systems. Many important applications are memory bound and others are expected to become memory bound in the future. The importance of memory performance makes it imperative to understand and optimize the interactions between applications and the system architecture. Prototyping and exploring various configurations of memory systems can give important insights, but current memory interfaces are limited in the amount of flexibility they provide. This inflexibility stems primarily from the fixed timing of the memory interface. Packetized memory interfaces abstract away the underlying timing characteristics of the memory technology and allow greater flexibility in the design of memory hierarchies. This work uses packetized interfaces to explore memory hierarchy designs and prototype a novel network attached memory. Since current processors do not support packetized memory interfaces, a coherent processor bus is used as a memory interface for the DiskRAM project. The Hybrid Memory Cube (HMC) packetized memory interface is also presented and used to prototype network-attached memory. The HMC interface is discussed in detail, along with the design and implementation of a Universal Verification Component (UVC) environment. The convergence of network and memory interfaces is also predicted.

Item Type: Dissertation
Supervisor: Brüning, Prof. Dr. Ulrich
Date of thesis defense: 9 February 2015
Date Deposited: 09 Mar 2015 10:37
Date: 2015
Faculties / Institutes: The Faculty of Mathematics and Computer Science > Department of Computer Science
Subjects: 004 Data processing Computer science
Controlled Keywords: Memory, Interconnect Networks, Storage
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