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Abstract

The upcoming High-Luminosity LHC (HL-LHC) upgrade of the Large Hadron Collider (LHC), will result in an average pileup of hμi = 200 proton-proton collisions per bunch-crossing. This is an unprecedented challenge for the Trigger and Data Acquisition Systems (T-DAQs) of the main experiments. Since track triggers are less susceptible to high-pileup than calorimeter triggers, a track trigger was developed for a low level of the ATLAS T-DAQ. The Linearized Track Fit (LTF) is a non-iterative algorithm that reconstructs the goodness and helix parameters of track candidates based on a linear approximation around a reference track solution. It requires minimal computational resources but a large amount of fast memory to store the linearizations of the reference tracks. Furthermore, it is highly parallel because it processes every helix parameter of every track candidate independently and with constant runtime. Therefore, it is uniquely well suited for implementation on parallel hardware. The Hardware Track Trigger (HTT) is a flexible custom hardware system that contains a full track reconstruction workflow; It was developed to be able to serve as both a low level track trigger and a track reconstruction coprocessor for the event filter. The basic building block of the HTT is the Pattern Recognition Mezzanine (PRM), which consists of a single large Field Programmable Gate Array (FPGA) that runs the LTF and holds the linearization constants in a High-Bandwidth Memory (HBM) as well as several Associative-Memory ASICs (AM-ASICs) that perform pattern recognition. This study presents the finalization of the PRM firmware development, particularly the implementation of the Track Fitter Block (TF), of the AM-ASIC interface, and of the HBM Interface (HBM-IF). The PRM was confirmed to run on prototype hardware using an Intel Altera Stratix 10 MX 2100 FPGA (Intel Stratix 10) FPGA and custom made emulators for the AM-ASICs. The track fitting quality (fit goodness, parameter resolution, and reconstruction accuracy), trigger quality (efficiency and purity), and the technical performance (latency, throughput, and resource usage) were evaluated using register transfer level (RTL) simulations. Additionally, the LTF was implemented on an Nvidia Tesla T4 GPU (Nvidia T4) Graphics Processing Unit (GPU) to investigate which hardware architecture is better suited to the algorithm. The results of those implementations are compared to pure software results and to the results of a completely different track fitting algorithm, the General Triplet Track Fit (GTTF). This study found that it is possible to implement an LTF track fitter on the Intel Stratix 10 so that it fulfills the HTT baseline requirements for the event filter scenario. As of now, the latency target of 1 μ s for the low level scenario was missed by 30 %. Because of its exceptionally low computational demands and its reliance on fast memory access and wide connections, the LTF has been found to be best suited to be implemented on a large number of low performance GPUs. This enables a cost effective track trigger architecture using consumer-grade or even outdated devices. This study successfully demonstrates the feasibility of hardware-accelerated track reconstruction for next-generation particle physics experiments and the multi-platform evaluation offers valuable insights into the trade-offs between different computing architectures for high-throughput scientific computing applications. The study contributes both to the immediate needs of ATLAS and to the broader field of real-time data processing in scientific applications, establishing a foundation for future developments in hardware-accelerated track reconstruction.