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Abstract

The intention of this dissertation was the development of a multi-channel mixedsignal detector readout ASIC. This paper describes the whole design process that starts with the vague requirement for a readout chip for some CBM/FAIR sub-detector and that ends with the latest and actually realized system on a chip solution called SPADIC, which is mainly intended to read out the future CBM-TRD. This work comprises the design from scratch of 6 ASIC prototypes and 10 PCB readout setups as well as the development of various software and firmware components, the characterization of the designed ASICs, the development of the SPADIC concept, the design of the SPADIC website, and not at least the collaboration with the TRD physicists with the achieved goal to read out signals of chamber prototypes using different SPADICs during CERN beam-times or in the laboratory. Besides the descriptions of the most important chip details and the corresponding theoretical analyses, an overall introduction into detectors and detector physics – written on a level for engineers – is given in this paper in order to embed this technical work into its physical context. The effective output of this dissertation is the self-triggered 32-channel charge pulse amplification and digitization chip SPADIC 1.0.