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Von Neumann bottlenecks in non-von Neumann computing architectures

Karasenko, Vitali

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Abstract

The term "neuromorphic" refers to a broad class of computational devices that mimic various aspects of cortical information processing. In particular, they instantiate neurons, either physically or virtually, which communicate through time-singular events called spikes. This thesis presents a generic RTL implementation of a Point-to-Point chip interconnect protocol that is well-suited to accommodate the unique I/O requirements associated with event-based communication, especially in the case of accelerated mixed-signal neuromorphic devices. A physical realization of such an interconnect was implemented on the most recent version of the BrainScaleS-2 architecture---the HICANN-X system---to facilitate a high-speed bi-directional connection to a host FPGA. Event rates of up to 250MHz full-duplex as well as several stream-secured configuration and memory interface channels are transported via 8*1Gbit/s LVDS DDR serializers. As the presented approach is entirely independent of the serializer implementation, it has applications beyond neuromorphic computing, such as enabling the separation of concerns and aiding the development of serializer-independent protocol bridges for system design.

Item Type: Dissertation
Supervisor: Schemmel, Dr. Johannes
Place of Publication: Heidelberg
Date of thesis defense: 27 May 2020
Date Deposited: 04 Aug 2020 13:53
Date: 2020
Faculties / Institutes: The Faculty of Physics and Astronomy > Kirchhoff Institute for Physics
Subjects: 004 Data processing Computer science
530 Physics
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